The present invention relates to semiconductor devices, and manufacturing methods thereof, and more particularly, to a manufacturing method of a semiconductor device using a damascene technique, and a semiconductor device manufactured by the method.
A plurality of semiconductor elements formed in a semiconductor substrate are electrically coupled to each other, for example, by multilayer wiring to form a predetermined circuit. With miniaturization of the semiconductor element, an embedded wiring structure has been developed as a wiring structure. The embedded wiring structure is formed by embedding wiring material in a wiring trench formed in an insulating film, or in a wiring opening, such as a hole, by the damascene technique. The damascene technique includes a single damascene process, and a dual damascene process.
For example, Patent Document 1 has proposed a technique in which a copper wiring is formed by the damascene technique in a three-layered structure including an insulating film, such as a silicon nitride film, a silicon oxide nitride film, a silicon carbide film, or a silicon carbide-nitride film, another insulating film formed thereon and comprised of organic polymer low-dielectric constant insulating material, and a further insulating film formed thereon, such as a silicon nitride film, a silicon carbide film, or a silicon carbide-nitride film. Patent Document 2 has proposed a technique for controlling a composition of carbon of a SiOC film having a copper wiring formed by the damascene technique.
Patent Document 3 discloses a manufacturing method of a semiconductor device which includes the steps of embedding siloxane SOG in between gate electrodes by a coating method, forming a fluorinated silicone oxide film on the siloxane SOG by a plasma CVD method, and forming a contact hole reaching a semiconductor substrate through the siloxane SOG and the fluorinated silicone oxide film. The manufacturing method further includes the steps of forming a fluorinated polyimide film over the fluorinated silicon oxide film by the coating method, forming a wiring trench reaching the fluorinated silicon oxide film by etching the fluorinated polyimide film according to a wiring trench pattern, and embedding conductive material in the contact hole and the wiring trench to form wirings.
Patent Document 4 discloses a semiconductor device with an aluminum multilayer wiring structure, and proposes a technique for holding aluminum wiring by a SiON film formed by the plasma CVD method so as to prevent harmful influence on insulation resistance or the like of the aluminum wiring due to moisture absorbed from the air by a SiOF film serving as an interlayer film formed by the plasma CVD method.
Patent Document 5 discloses a wiring layer structure including an ozone TEOS (tetraethoxysilane) film as an lower layer, and a plasma oxide film as an upper layer. Patent Document 6 discloses a technique for forming a moisture-resistant multilayer interlayer film by forming a silicon oxide film as an interlayer insulating film on a thermal CVD film including organic silane and ozone by the plasma CVD method. Patent Document 7 discloses a technique for forming silicon rich oxide films above and under a plasma CVD film containing fluorine serving as a low dielectric constant film in a wiring layer so as to prevent diffusion of fluorine from the plasma CVD oxide film containing the fluorine. Further, Patent Document 8 discloses a structure including moisture-resistant insulating films (of silicon nitride) formed in upper and lower positions of a wiring layer, and a hygroscopic ozone TEOS film formed therebetween.
After forming a semiconductor element, such as a metal insulator semiconductor field effect transistor (MISFET), over a main surface of a semiconductor substrate, an interlayer insulating film is formed over the main surface of the semiconductor substrate so as to cover the semiconductor element. In recent years, a gap between gate electrodes of the MISFETs has become smaller with miniaturization of the semiconductor elements. An insulating film having good embedded properties into between the gate electrodes or the like is desired to be used in such an interlayer insulating film. The insulating film formed by the plasma chemical vapor deposition (CVD) method has the low embedded properties, and thus cannot be surely embedded in a space between the gate electrodes when the space therebetween is relatively narrow, which may generate voids. In contrast, an insulating film, such as an O3-TEOS (tetraethoxysilane) oxide film, formed by the thermal CVD, or an insulating film, such as the spin on glass (SOG) film, formed by the coating method has good embedded properties into a space between the gate electrodes or the like.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2005-136152    [Patent Document 2] Japanese Unexamined Patent Publication No. 2005-223021    [Patent Document 3] Japanese Unexamined Patent Publication No. Hei 11(1999)-87510    [Patent Document 4] Japanese Unexamined Patent Publication No. Hei 6(1994)-302704    [Patent Document 5] Japanese Unexamined Patent Publication No. Hei 7(1995)-153840    [Patent Document 6] Japanese Unexamined Patent Publication No. Hei 5(1993)-109910    [Patent Document 7] Japanese Unexamined Patent Publication No. Hei 11(1999)-317454    [Patent Document 8] Japanese Unexamined Patent Publication No. Hei 6(1994)-53210